The present invention relates to a flash memory.
Non-volatile memory devices, such as electronically erasable programmable read only memories (EEPROMs) and erasable programmable read only memories (EPROM), are widely used in data processing systems to retain data information even when the power is removed. One specific type of EEPROM is a flash EEPROM, wherein data stored therein is erased in blocks, instead of on a byte level. For example, if a byte in a block must be changed, the entire block must be erased and reprogrammed.
Flash memories are commonly used in a wide range of embedded applications, that is, systems in which a controller is employed as the primary control chip in an electronic circuit embedded in a product other than a general purpose computer system. The flash memory is generally used to store control codes and operational parameters, such as error reporting thresholds and system states. When the information in the flash memory changes, the controller updates the data by erasing and reprogramming the blocks affected in the flash memory. In such systems, the flash memory device and controller may be physically located on different circuit packs. Since the two devices are located on separate circuit packs they may be unplugged or removed independently from one another. If the controller is unplugged or removed before completion of the reprogramming operation of the flash memory, then the data therein will be corrupted.
One known solution to this problem is to provide a reset button on the board. By enabling the reset button, a timer is set for a predefined period of time. Upon expiration of the predefined period of time, the software timer interrupt handler starts the reset sequence and the control circuit pack may be unplugged. This solution assumes that the reprogramming of the flash memory will be completed during the predefined period of time. Although the timer usually ensures that the flash memory has finished programming one block within the predefined period, reprogramming of a second block of the flash memory may already be in progress when the predefined period of time expires and the reset sequence is started. In this situation, if the control circuit pack is unplugged the data in the second block of memory will be corrupted.
The present invention is an embedded system that overcomes these problems and prevents removal of the control circuit pack during programming of the flash memory.
In particular, the present invention is directed to an embedded system for preventing removal of a control circuit pack during programming of a flash memory. The embedded system includes a reset button for invoking a reset interrupt and an indicator for signaling when the control circuit pack may be safely removed or unplugged from a shelf. In the case in which programming of the flash memory is uninterruptable, all of the interrupts, except for a power reset interrupt, are inhibited during programming of at least one block of the flash memory. Before unplugging the flash memory from the shelf, a reset button is pressed. If programming of the flash memory is in progress, then upon activating the reset button the reset interrupt, like all other interrupts, is inhibited. Otherwise, if the reset interrupt is invoked, an indicator signaling the completion of programming of the flash memory is enabled.
Alternatively, if programming of the flash memory is interruptable, then none of the interrupts are inhibited during programming of the flash memory. In this case the system also includes a timer interrupt automatically invoked after a timer has completed a countdown of a predefined time interval. During programming predetermined interrupts, except for the reset interrupt or the timer interrupt, that require processor time that exceeds the programming time required, are inhibited. In response to invoking a reset interrupt, if programming of the flash memory is in progress, then the time is set to countdown for the predefined time interval and return from the interrupt to resume programming from the position of interruption. Completion of the countdown invokes a timer interrupt handler that continuously resets the timer to countdown for the predefined time interval and upon completion of the countdown, determines whether programming of the flash memory is in progress. The indicator is enabled when programming of the flash memory is no longer in progress.